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Vijaykrishnan Narayanan
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Vijaykrishnan Narayanan

  • Co-Director: Microsystems Design Lab (MDL)
  • Distinguished Professor
354D IST Building
University Park, PA 16802
Phone: (814) 863-0392


  1. Ph.D., University of South Florida, Tampa


Vijaykrishnan Narayanan is currently at the Computer Science and Engineering and Electrical Engineering Departments at Penn State. He is a member of the Embedded and Mobile Computing Design Center and his research/teaching interests are in the areas of energy-aware reliable systems, embedded systems, on-chip networks, system design using emerging technologies (3D and Nano) and computer architecture. His research is supported by grants from National Science Foundation, The Technology Collaborative, and DARPA.

Dr. Narayanan along with his collaborators have developed various energy estimation tools and power models that have been widely used. He also leads an interdisciplinary project funded by NSF that has set up a one-of-a-kind accelerated soft-error testing facility at the Penn State Nuclear reactor. He and his students interact closely with industry partners (Intel, IBM, Xilinx, Videomining Corp, and Sun Microsystems) in addressing critical research issues. Narayanan has worked with 15 Ph.D. students, 25 M.S. students, and 5 undergraduate honors students. His former students currently work in leading companies and universities in different countries around the world.

Dr. Narayanan has received several awards including the Penn State Engineering Society Outstanding Research Award in 2006, IEEE CAS VLSI Transactions Best Paper Award in 2002, the Penn State CSE Faculty Teaching Award in 2002, the ACM SIGDA outstanding new faculty award in 2000, Upsilon Pi Epsilon award for academic excellence in 1997, the IEEE Computer Society Richard E. Merwin Award in 1996 and the University of Madras first rank in Computer Science and Engineering in 1993.

Dr. Narayanan is actively involved with various technical service activities. He served as general co-chair, ISVLSI 2002; general-chair, ISVLSI 2003; vice-general chair, Nanonets 2007, and as program co-chair for GLSVLSI 2006, Nanonets 2006, and ISLPED 2007. He serves on the steering committees of ISVLSI and GLSVLSI conferences.

He is currently the editor-in-chief of the ACM Journal on Emerging Technologies in Computing Systems. He also serves on editorial boards of IEEE Transactions on CAD and the Journal of Low Power Electronics. He served as the vice-chair for student activities for IEEE Computer Society from 2000-2006 and as a Chapter representative on the IEEE Student Activities Committee from 2004-2006. He has received several certificates of appreciation for outstanding service from ACM and IEEE Computer Society.

Research Interests:

Energy-Aware and Reliable Systems, Embedded Java, Nano/VLSI Systems, Computer Architecture

Selected Publications:

  1. Irick, K., M. DeBole, N. Vijaykrishnan, R. Sharma, H. Moon, S. Mummareddy. August 2007. Unified Streaming Architecture for Real Time Face Detection and Gender Classification. Proceedings of the Seventeenth International Conference on Field Programmable Logic and Applications (FPL 2007). pp. 267-272.  Amsterdam, Netherlands.
  2. Kim, J., C. Nicopoulos, D. Park, R. Das, Y. Xie, N. Vijaykrishnan, C. R. Das. June 2007. A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures. Proceedings of the Thirty-Fourth Annual International Symposium on Computer Architecture (ISCA 2007). pp. 138-149. San Diego, CA.
  3. Mutyam, M., N. Vijaykrishnan. April 2007. Working with Process Variation Aware Caches. Proceedings of the Design, Automation and Test in Europe (DATE'07). pp. 1152-1157. Nice, France.
  4. Srinivasan, S., P. Mangalagiri, K. Sarpatwari, Y. Xie, N. Vijaykrishnan. July 2006. FLAW: FPGA Lifetime Awareness. Proceedings of the Design Automation Conference (DAC 2006). pp. 630-635. San Francisco, CA.
  5. Duarte, D., N. Vijaykrishnan, M. J. Irwin. December 2002. A Clock Power Model to Evaluate Impact of Architectural and Technology Optimizations. IEEE Transactions on VLSI 10(6):844-855. (IEEE CAS TRANSACTIONS ON VLSI BEST PAPER AWARD)