Mary Jane Irwin

Mary Jane Irwin received the M.S. (1975) and Ph.D. (1977) degrees in computer science from The University of Illinois, Urbana-Champaign. Dr. Irwin has been on the faculty at Penn State since 1977. She received an Honorary Doctorate from Chalmers University, Sweden, in 1997 and the Penn State Engineering Society's Premier Research Award in 2001. She was awarded the ACM Distinguished Service Award and the CRA Distinguished Service Award, both in 2006. Dr. Irwin was named a Fellow of IEEE in 1995, a Fellow of ACM in 1996, was elected to the National Academy of Engineering in 2003. She was named the A. Robert Noll chair of Engineering in 2003 and an Evan Pugh Professor in 2006.

Dr. Irwin co-leads (with Drs. Kandemir, Narayanan, and Xie) the Microsystems Design Lab with a focus on power and reliability aware design, embedded and mobile computing systems design, and emerging technologies in computing. Their research is supported by the National Science Foundation, the FCRP, Gigascale Systems Research Center, the Semiconductor Research Corporation, Intel Corporation, and Microsoft.

Dr. Irwin is also collaborating with Dr. Raghavan in the development of adaptive software tools to co-manage quality-performance-power tradeoffs in large-scale scientific simulations.

Research Interests:

Computer Architecture, Embedded and Mobile Computing Systems Design, Power Aware Design, Emerging Technologies in Computing Systems

Selected Publications:

1. Ozturk, O., M. Kandemir, M. J. Irwin, S. Tosun. July 2006. Multi-level On-chip Memory Hierarchy Design for Embedded Chip Multiprocessors. Proceedings of the Twelfth International Conference on Parallel and Distributed Systems (ICPADS'06). pp. 383-390. Minneapolis, MN. (Conference best paper award)
   
2. Degalahal, V., L. Li, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. October 2005. Soft Error Issues in Low-Power Caches. IEEE Transactions on VLSI 13(10):1157-1166.
   
3. Kim, N., T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, N. Vijaykrishnan. December 2003. Leakage Current: Moore's Law Meets Static Power. IEEE Computer, Special Issue on Power- and Temperature-Aware Computing 36(12):68-75.
   
4. Vijaykrishnan, N., M. Kandemir, M. J. Irwin, H. Kim, W. Ye. January 2003. Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework. Transactions on Computers 52(1):59-76.
   
5. Duarte, D., N. Vijaykrishnan, M. J. Irwin. December 2002. A Clock Power Model to Evaluate Impact of Architectural and Technology Optimizations. IEEE Transactions on VLSI 10(6):844-855.