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Mary Jane Irwin
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Mary Jane Irwin

  • Co-Director: Microsystems Design Lab (MDL)
  • Robert E. Noll Professor
  • Evan Pugh Professor
348C IST Building
University Park, PA 16802
Phone: (814) 865-1802

Education:

  1. Ph.D., University of Illinois at Urbana-Champaign

Biography:

Mary Jane Irwin received the M.S. (1975) and Ph.D. (1977) degrees in computer science from The University of Illinois, Urbana-Champaign. Dr. Irwin has been on the faculty at Penn State since 1977. She received an Honorary Doctorate from Chalmers University, Sweden, in 1997 and the Penn State Engineering Society's Premier Research Award in 2001. She was awarded the ACM Distinguished Service Award and the CRA Distinguished Service Award, both in 2006 and won ACM's Athena Award in 2010. Dr. Irwin was named a Fellow of IEEE in 1995, a Fellow of ACM in 1996, was elected to the National Academy of Engineering in 2003, and was elected to the American Academy of Arts and Science in 2009.  She was named the A. Robert Noll chair of Engineering in 2003 and a Penn State Evan Pugh Professor in 2006.

Dr. Irwin co-leads (with Drs. Kandemir, Narayanan, and Xie) the Microsystems Design Lab with a focus on power and reliability aware design, embedded and mobile computing systems design, and emerging technologies in computing. Their research is supported by the National Science Foundation, the FCRP, Gigascale Systems Research Center, the Semiconductor Research Corporation, Intel Corporation, and Microsoft.

Dr. Irwin is also collaborating with Dr. Raghavan in the development of adaptive software tools to co-manage quality-performance-power tradeoffs in large-scale scientific simulations.

Research Interests:

Computer Architecture, Embedded and Mobile Computing Systems Design, Power Aware Design, Emerging Technologies in Computing Systems

Selected Publications:

  1. Kandemir, M., T. Yemliha, S. Muralidhara, S. Srikantaiah, M. J. Irwin, Y. Zhang.  June 2010.  Cache Topology Aware Computation Mapping for Multicores.  Proceedings of the ACM SIGPLAN 2010 Conference on Programming Language Design and Implementation (PLDI 2010).  pp. 74-85.  Toronoto, Canada.
  2. Tsai, Y., F. Wang, Y. Xie, N. Vijaykrishnan, M. J. Irwin.  April 2008.  Design Space Exploration for Three-Dimensional Caches.  IEEE Transactions on VLSI 16(4):444-455.
  3. Ding, Y., M. Kandemir, P. Raghavan, M. J. Irwin.  April 2008.  A Helper Thread Based EDP Reduction Scheme for Adapting Application Execution in CMPs.  Proceedings of the Twenty-Second IEEE International Parallel and Distributed Processing Symposium (IPDPS 2008).  14 pages.  Miami, FL.  (Best Paper Award, Software Track)
  4. Ozturk, O., M. Kandemir, M. J. Irwin, S. Tosun. July 2006. Multi-level On-chip Memory Hierarchy Design for Embedded Chip Multiprocessors. Proceedings of the Twelfth International Conference on Parallel and Distributed Systems (ICPADS'06). pp. 383-390. Minneapolis, MN. (Conference best paper award)
  5. Kim, N., T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, N. Vijaykrishnan. December 2003. Leakage Current: Moore's Law Meets Static Power. IEEE Computer, Special Issue on Power- and Temperature-Aware Computing 36(12):68-75.
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