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# CSE 575/577

Computer Arithmetic, and CSE 577, Advanced VLSI Systems Design

### The Pennsylvania State University, University Park, PA, 16802

In this class we will use extensively Cadence First Encounter v. 4.1, in conjunction with OKI and TSMC's standard cell libraries to design ASICs for various small-scale projects. We will learn how to go from the RTL level all the way to the floor-planning and layout level. We will use First Encounter to lay the functional blocks, generate the power grids, generate the clock tree and finalize the design for manufacturing.

USEFUL INFO:

Please DO NOT print the manuals. Try to use the online manuals as far as possible.

The OKI technology we are using is 0.16um. The 0.16um refers to the effective gate width of a CMOS transistor and not the gate size itself.

In its area estimations Synopsys Design Compiler uses as a unit of area the size of the "normalized" 2-Input NAND Gate. In other words a 2-Input NAND gate will fit/fill one "SLOT" of the ASIC. All other cells are referenced to this cell/size. The area of a NAND gate is = 1. If a cell has a size = 4, then it is 4x larger than the NAND gate. In the case of our OKI library the physical size of 2-input NAND gate is 1.56um x 5.2um. So, for example is a certain cell in the library has a normalized size of 4, its physical size would be 6.24 x 5.2 (x and y dimensions, respectively).

The y dimension typically does not change since this is the ROW height. The x dimension is the variable dimension since you can expand the cells width without making the cell any taller. So, to get a true area calculation a NAND gate would be 1.56um x5.2um = 8.112 square microns.

Of course, the true chip area cannot be calculated just from area estimation for all cells in the design since filler cells, area between cell rows, routing channels also have to be considered. All these factors finalize after placement and routing stage.

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