1. Interconnection Networks HPCL lab is known for its pioneering research in the area of design and
analysis of interconnection networks for multiprocessors. Specifically,
people in the HPCL lab have made fundamental contributions over the
last 25 years across a broad range of topics spanning design of
switch/router architectures, network topology, routing mechanisms,
fault-tolerance, performance and dependability
(reliability/availability) evaluation of interconnection networks.
More recently, graduate students in the HPCL lab have been focusing on
on-chip interconnection networks or Network-on-Chip (NoC), widely viewed
as the de-facto enabler for scalable multicore systems. On-die hardware implementation and manufacturing constraints impose a different tradeoff
domain for NoCs when compared to traditional off-chip networks. In the
NoC domain, power consumption, chip area, and fabrication complexity are
considered to be the first-class constraints. These and few other design
constraints lead to architecting NoCs a challenging problem when
compared to traditional and well-understood multiprocessor networks. In
this context, currently, people in the HPCL lab are conducting research
on router microarchietcture, 3D NoCs, low power interconnection
networks, fault tolerant NoCs, co-designing NoCs with novel memory
technologies, co-design of processor, memory heirarchy and NoCs, and
application aware design of NoCs.
2. Data Centers & Clouds
HPCL lab covers multi-faceted research in the areas of large scale distributed systems like Internet data centers and Clouds. The main research thrust here can be broadly classified into these sub-categories: (a) Performance and power management of multi-tier data centers; (b) Characterization and modeling of generic workloads in representative cloud compute clusters like those found in Google data centers. The focus here is to quantify the scheduling performance impacts of various cloud workload properties like resource usage and categories of jobs, task placement constraints, etc; (c) Efficient management and scheduling of resources in large server farms, hosting massive data-intensive frameworks like MapReduce; (d) Performance modeling and QoS of applications running in shared resource environments as in utility clouds; (e) Fault tolerance and failure diagnosis in virtualized cloud environments; (f) Virtualization: modeling and quantifying the performance impact of VM live migrations; resource management in virtualized data centers.
3. Emerging Memory Technology STTRAM is one of the emerging non-volatile memory technology which has the
potential to replace conventional on-chip SRAM cache. Its high density, low leakage and, resistance to bit-flips/errors
makes it very attractive, however its long write latency and energy are the major obstacles for being competive with SRAM-based cache hierarchy.
In our lab, we see how to architect the cache hierachy with STT-RAM by combating/hiding its negative points.
4. Heterogeneous Architectures The term heterogenous is an overloaded term, but it is for good and architecting these big systems can be immensely difficult.
In our lab, we look how to develop QoS aware, power effecient and high performing systems when many cores, small cores, CPUs, acclerators,
GPUs reside on same chip. We mainly focus on desiging cache hierarchy, NoC and memory hierarchy for these systems.
5. Soft Computing
Inaccuracy in computation has usually been considered with a negative connotation.
Unconventionally, in our lab, we try to capitalize on several application's tolerance level to inaccuracy or approximation.
We develop techniques for facilitating soft-computing or approximate computing to achieve significant power and performance gain.
Our results will have tremendous impact on future HPC/exascale systems.
3. Emerging Memory Technology
4. Heterogeneous Architectures