Conference Program

 

Sunday, January 10, 2010

 

6:00-8:00pm: Inaugural Event

 

Monday, January 11, 2010

7:00-7:45am: Breakfast [at conference hotels]

 

8:40-9:00am: Welcome Messages (Joint HPCA/PPoPP)

 

8:50-10:00am: Keynote Session I (Joint HPCA/PPoPP):

Chairs: Chita Das, Pennsylvania State University, Pradip Bose, IBM T. J. Watson Research Center

Exascale Computing: The challenges and opportunities in the next decade

Tilak Agerwala, VP Systems, IBM Research

 

10:00-10:20am Break

 

10:20-12:00am: Session 1: Best Paper Nominees
Chair:
Yale Patt, University of Texas at Austin


10:20-10:45: Value Based BTB Indexing (VBBI) for Indirect Jump Prediction  
Muhammad Umar Farooq,
University of Texas at Austin,

Lei Chen, University of Texas at Austin

Lizy K. John, University of Texas at Austin

 

10:45-11:10: Operating System Support for Overlapping-ISA Heterogeneous Multi-Core Architectures
Tong Li,
Intel Corporation

Paul Brett, Intel Corporation

Rob Knauerhase, Intel Corporation

David Koufaty, Intel Corporation

Dheeraj Reddy, Intel Corporation

Scott Hahn, Intel Corporation

 

11:10-11:35: Scalable Architectural Support for Trusted Software
David Champagne, Princeton University
Ruby Lee, Princeton University

11:35-12:00: ATLAS: A Scalable and High Performance Scheduling Algorithm for Multiple Memory Controllers

Yoongu Kim, Carnegie-Mellon University
Dongsu Han, Carnegie-Mellon University
Onur Mutlu, Carnegie-Mellon University

Mor Harchol-Balter, Carnegie-Mellon University

12:00-1:30pm: Lunch

 

1:30-3:30pm: Session 2A: Multicore Architectures
Chair:
James Laudon, Google


1:30-1:55: Understanding How Off-Chip Memory Bandwidth Partitioning in Chip Multiprocessors Affects System Performance
Fang Liu,
North Carolina State University
Xiaowei Jiang, North Carolina State University
Yan Solihin, North Carolina State University

1:55-2:20: LeadOut: Composing Low-Overhead Frequency-Enhancing Techniques for Single Thread Performance in Configurable Multicores
Brian Greskamp,
University of Illinois at Urbana-Champaign
R. Ulya Karpuzcu, University of Illinois at Urbana-Champaign
Josep Torrellas, University of Illinois at Urbana-Champaign

2:20-2:45: LiteTM: Reducing Transactional State Overhead
Syed Ali Raza Jafri,
Purdue University

Mithuna Thottethodi, Purdue University

T. N. Vijaykumar, Purdue University

 

2:45-3:10: A Bandwidth-Aware Memory Subsytem Resource Management Using Non-Invasive Resource Profilers for Large CMP Systems
Dimitris Kaseridis,
University of Texas at Austin
Jeffrey Stuecheli, IBM Corporation and University of Texas at Austin
Lizy K. John, University of Texas at Austin

3:10-3:30: Buffer that can be used for Q&A, discussion spanning all papers in the session, moderated by the session chair.

1:30-3:30pm: Session 2B: Reliability and Energy Efficiency
Chairs: Murali Annavaram,
University of Southern California, Ruby Lee, Princeton University


1:30-1:55: HARE: Hardware Assisted Reverse Execution
Ioannis Doudalis,
Georgia Institute of Technology
Milos Prvulovic, Georgia Institute of Technology

1:55-2:20: Designing a Processor From the Ground Up to Allow Voltage/Reliability Tradeoffs
Andrew Kahng,
University of California at San Diego (UCSD)
Seokhyeong Kang, University of California at San Diego (UCSD)
Rakesh Kumar, University of Illinois at Urbana-Champaign (UIUC)

John Sartori, University of Illinois at Urbana-Champaign (UIUC)

 

2:20-2:45: IADVS: On-Demand Performance for Interactive Applications

Mingsong Bi, University of Arizona

Igor Crk, University of Arizona

Chris Gniady, University of Arizona

 

2:45-3:10: A Hybrid Solid-State Storage Architecture for Performance, Energy Consumption and Lifetime Improvement
Guangyu Sun,
Pennsylvania State University

Yongsoo Joo, Pennsylvania State University
Yibo Chen,
Pennsylvania State University
Yuan Xie,
Pennsylvania State University
Yiran Chen,
Seagate

Helen Li, Seagate

 


3:10-3:30: Buffer that can be used for Q&A, discussion spanning all papers in the session, moderated by the session chair.

3:30-4:00pm: Break

4:00-5:30pm: Panel (joint with PPoPP):

Extreme Scale Computing: Challenges and Opportunities
Moderator: Josep Torrellas, University of Illinois at Urbana-Champaign

Panelists: Bill Gropp, University of Illinois at Urbana-Champaign

Vivek Sarkar, Rice University

Jaime Moreno, IBM T. J. Watson Research Center

Kunle Olukotun, Stanford University

 

5:30-6:00pm: Break

6:00-7:00pm: TCCA Business Meeting

7:30-9:00pm: Dinner

Tuesday, January 12, 2010

 

8:50-10:00am: Keynote Session II (Joint HPCA/PPoPP):

Chairs: Keshav Pingali, University of Texas at Austin, R. Govindarajan, IISc, Bangalore

Is Hardware Innovation Over?

Arvind, Johnson Professor, Massachusetts Institute of Technology (MIT)

 

10:00-10:30am: Break

10:30am-12:00pm: Session 3: Memory Systems
Chair:
Onur Mutlu, Carnegie-Mellon University


10:30-10:55: Improving Read Performance of Phase Change Memories via Write Cancellation and Write Pausing
Moinuddin K. Qureshi,
IBM T. J. Watson Research Center
Michele Franceschini, IBM T. J. Watson Research Center

Luis Lastras, IBM T. J. Watson Research Center

 

10:55-11:20: DMA++: On the Fly Data Realignment for On-Chip Memories
Nikola Vujic,
Barcelona Supercomputing Center
Marc Gonzalez, Technical University of Catalonia

Felipe Cabarcas, Barcelona Supercomputing Center

Alex Ramirez, Barcelona Supercomputing Center

Xavier Martorell, Barcelona Supercomputing Center

Eduard Ayguade, Barcelona Supercomputing Center

 

11:20-11:45: Delay-Hiding Energy Management Mechanisms for DRAM

Mingsong Bi, University of Arizona

Ran Duan, University of Arizona

Chris Gniady, University of Arizona

 


11:45-12:00: Buffer that can be used for Q&A, discussion spanning all papers in the session, moderated by the session chair.

12:00-1:30pm: Lunch

 

1:30-3:30pm: Session 4A: Cache Architectures
Chair:
Viji Srinivasan, IBM T. J. Watson Research Center


1:30-1:55: Unified Instruction/Translation/Data (UNITD) Coherence: One Protocol to Rule Them All
Bogdan F. Romanescu,
Duke University

Alvin R. Lebeck, Duke University

Daniel J. Sorin, Duke University

Anne Bracy, Intel Corporation

1:55-2:20: StimulusCache: Boosting Performance of Chip Multiprocessors with Excess Cache
Hyunjin Lee,
University of Pittsburgh
Sangyeun Cho,
University of Pittsburgh
Bruce R. Childers, University of Pittsburgh


2:20-2:45: ESP-NUCA: A Low-Cost Adaptive Non-Uniform Cache Architecture

Javier Merino, Universidad de Cantabria

Valentin Puente, Universidad de Cantabria

Jose-Angel Gregorio, Universidad de Cantabria

 

2:45-3:10: CHOP: Adaptive Filter-Based DRAM Caching for CMP Server Platforms

Xiaowei Jiang, North Carolina State University

Niti Madan, University of Utah (now at IBM Research)

Li Zhao, Intel Corporation

Mike Upton, Intel Corporation

Ravishankar Iyer, Intel Corporation

Srihari Makineni, Intel Corporation

Donald Newell, Intel Corporation

Yan Solihin, North Carolina State University

Rajeev Balasubramonian, University of Utah

 


3:10-3:30: Buffer that can be used for Q&A, discussion spanning all papers in the session, moderated by the session chair.

 

1:30-3:30pm: Session 4B: On-chip Networks and IO
Chair:
Vijay Narayanan, Pennsylvania State University


1:30-1:55: Towards Scalable, Energy-Efficient Bus-Based On-Chip Networks
Aniruddha N. Udipi,
University of Utah
Naveen Muralimanohar, HP Labs
Rajeev Balasubramonian,
University of Utah

1:55-2:20: Simple Virtual Channel Allocation for High Throughput and High Frequency On-Chip Routers
Yi Xu,
University of Pittsburgh
Bo Zhao,
University of Pittsburgh
Youtao Zhang,
University of Pittsburgh

Jun Yang, University of Pittsburgh

2:20-2:45: High Performance Network Virtualization with SR-IOV
Yaozu Dong,
Intel Corporation

Xiaowei Yang, Intel Corporation

Xiaoyong Li, Intel Corporation

Jian hui Li, Intel Corporation

Haibin Guan, Intel Corporation

Kun Tian, Intel Corporation

 

2:45-3:10: DMA Cache: Using On-Chip Storage to Architecturally Separate I/O Data from CPU Data for Improving I/O Performance

Dan Tang, ICT, Chinese Academy of Sciences

Yungang Bao, ICT, Chinese Academy of Sciences

Weiwu Hu, ICT, Chinese Academy of Sciences

Mingyu Chen, ICT, Chinese Academy of Sciences

 


3:10-3:30: Buffer that can be used for Q&A, discussion spanning all papers in the session, moderated by the session chair.

3:30-4:00pm: Break

 

4:00-6:00pm: Session 5A: System Architecture and Performance Evaluation
Chair:
Milos Prvulovic, Georgia Institute of Technology


4:00-4:25: Graphite: A Distributed Parallel Simulator for Large-Scale Multicores
Jason Miller,
Massachusetts Institute of Technology
Harshad Kasture, Massachusetts Institute of Technology
George Kurian, Massachusetts Institute of Technology

Charles Gruenwald, Massachusetts Institute of Technology

Nathan Beckmann, Massachusetts Institute of Technology
Christopher Celio, Massachusetts Institute of Technology

Jonathan Eastep, Massachusetts Institute of Technology

Anant Agarwal, Massachusetts Institute of Technology

4:25-4:50: Interval Simulation: Raising the Level of Abstraction in Architectural Simulation
Davy Genbrugge,
Ghent University
Stijn Eyerman,
Ghent University
Lieven Eeckhout,
Ghent University

4:50-5:15: Application Performance Modeling in a Virtualized Environment

Sajib Kundu, Florida International University

Raju Rangaswami, Florida International University

Kaushik Dutta, Florida International University

Ming Zhao, Florida International University

 

5:15-5:40: COMIC++: A Software SVM System for Heterogeneous Multicore Accelerator Clusters

Jaejin Lee, Seoul National University

Jun Lee, Seoul National University

Sangmin Seo, Seoul National University

Jungwon Kim, Seoul National University

Seungkyun Kim, Seoul National University

Zehra Sura, IBM T. J. Watson Research Center

 


5:40-6:00: Buffer that can be used for Q&A, discussion spanning all papers in the session, moderated by the session chair.

4:00-5:30pm: Session 5B: Processor Microarchitecture
Chair: Sriram Vajapeyam,
IBM India Research Laboratory, Lieven Eeckhout, Ghent University


4:00-4:25: BOLT: An Energy-Efficient Latency-Tolerant Processor

Andrew Hilton, University of Pennsylvania

Amir Roth, University of Pennsylvania

4:25-4:50: SIF: Overcoming the Limitations of SIMD Devices Via Implicit Permutation
Libo Huang,
National University of Defense Technology
Li Shen, National University of Defense Technology
Zhiying Wang, National University of Defense Technology

4:50-5:15: Handling Branches in TLS Systems with Multi-Path Execution
Polychronis Xekalakis,
University of Edinburgh
Marcelo Cintra, University of Edinburgh

 


5:15-5:30: Buffer that can be used for Q&A, discussion spanning all papers in the session, moderated by the session chair.

7:30-10:00pm: Conference Banquet

 

Wednesday, January 13, 2010

9:00-10:40am: Session 6: Industrial Perspectives
Chair: Ravishankar Iyer,
Intel Corporation, Smruti Sarangi, IBM India Research Laboratory

 

9:00-9:25: Explaining Cache SER Anomaly Using DUE AVF Measurement

Arijit Biswas, Intel Corporation

Charles Recchia, Intel Corporation

Shubhendu S. Mukherjee, Intel Corporation

Vinod Ambrose, Intel Corporation

Leo Chan, Intel Corporation

Aamer Jaleel, Intel Corporation

Athansios E. Papathanasiou, Intel Corporation

Mike Plaster, Intel Corporation

Norbert Seifert, Intel Corporation


9:25-9:50: Worth their Watts? An Empirical Study of Datacenter Servers

Arunchandar Vasan, Tata Consultancy Services
Anand Sivasubramaniam,
Tata Consultancy Services

Vikrant Shimpi, Tata Consultancy Services

T. Sivabalan, Tata Consultancy Services

Rajesh Subbiah, Tata Consultancy Services

9:50-10:15: High-Performance, Low-Vcc In-Order Core
Jaume Abella,
Intel Labs, Barcelona
Pedro Chaparro, Intel Labs, Barcelona
Xavier Vera, Intel Labs, Barcelona
Javier Carretero, Intel Labs, Barcelona
Antonio Gonzalez,
Intel Labs, Barcelona


10:15-10:40: Architecting for Power Management: The POWER7 Approach
Malcolm Ware,
IBM Austin Research Laboratory
Karthick Rajamani,
IBM Austin Research Laboratory

Michael Floyd, IBM Systems and Technology Group

Bishop Brock, IBM Systems and Technology Group

Juan C. Rubio, IBM Austin Research Laboratory

Freeman Rawson, IBM Austin Research Laboratory

John B. Carter, IBM Austin Research Laboratory

 

10:40-11:00am: Break

 

 

11:00am-12:00pm: Session 7: Architectures for Emerging Technologies
Chair:
Babak Falsafi, Ecole Polytechnique Federale de Lausanne (EPFL)


11:00-11:25: An Optimized 3D-Stacked Memory Architecture by Exploiting Excessive, High-Density TSV Bandwidth

Dong Hyuk Woo, Georgia Institute of Technology
Nak Hee Seong, Georgia Institute of Technology
Dean L. Lewis, Georgia Institute of Technology
Hsien-Hsin S. Lee, Georgia Institute of Technology

11:25-11:50: FlexiShare: Energy-Efficient Nanophotonic Crossbar Architecture through Channel Sharing
Yan Pan,
Northwestern University
John Kim, KAIST

Gokhan Memik, Northwestern University

11:50-12:00: Buffer that can be used for Q&A, discussion spanning all papers in the session, moderated by the session chair.

12:00-12:15pm: Presentation of Best Paper Award
Chair: Chita Das,
Pennsylvania State University, Matthew Jacob, IISc - Bangalore


12:15-1:30pm: Lunch

1:30 pm onwards : Free to explore Bangalore

Thursday, January 14, 2010

7:00-7:45am: Breakfast [at conference hotels]

 

8:00am to 9:00pm: Excursion: Heritage of Karnataka Tour
Lunch and Dinner will be provided

 

 

The 16th IEEE International Symposium on

Welcome to HPCA-16

High-Performance Computer Architecture

Bangalore, India - January 9-14, 2010

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