new Call for papers for ACM JETC Speciall issue on 3D ICs

Interconnects dominate the performance and power behavior of deep submicron designs. Consequently, interconnect centric design methods and technology improvements are critical to the chip industry. While there have been significant interconnect technology improvements over the last few years. The various technologies being actively explored to address the interconnect problem include the use of Three-dimensional Integrated Circuits (3D IC) and packet-based on chip communication networks (Network-on-Chip).

    A three dimensional (3D) chip is a stack of multiple device layers with direct vertical interconnects tunneling through them. A key benefit of this approach over a traditional two dimensional chip is the ability to reduce the length of long interconnects. Prior efforts have focused on developing different fabrication techniques involved in stacking multiple device layers and in forming the vertical interconnects. The size and density of the vertical interconnects that can tunnel between the different device layers varies based on the underlying technology used to fabricate the 3D chips.  To efficiently exploit the benefits of 3D technologies, design techniques and methodologies for supporting 3D designs are imperative.

3D EDA/Architecture Project Sponsors/Collaborators:

NSF, DARPA, IBM, Honda, Qualcomm, Seagate,IMEC

Tool Release:

Selected Publications:

Tutorial:   

Invited Talks on 3D IC:

11/2007 Qualcomm. San Diego, CA
  " 3D EDA and Architecture"  
10/2007 Seagate Technology LLC. Bloomington, MN
  " 3D IC Design Tutorial"  
10/2007 SEMATECH 3D workshop Albany, New York
  "3D Archtecture Design"  
09/2007 KAIST University Daejeon, Korea
  "Design Space Explorations for 3D ICs"  
05/2007 Honda Research Institute. Tokyo, Japan
  "Design Automation for Three-dimensional ICs"  
05/2007 Peking University Beijing, China
  "New Dimension for High Performance"  
04/2007 IMEC (Interuniversity Microelectronics Centre) Leuven, Belgium
  "The Challenges of Designing 3D Microarchitectures"  
01/2007 Dagstuhl Seminar on Power-Aware Computing Systems. Dagstuhl, Germany
  "Thermal Challenges in 3D Microarchitecture Design"  
11/2006 The 3rd Annual 3D Architecture Conference. San Francisco, CA
  "Design Space Exploration for 3D IC Design;  
10/2006 University of Pittsburgh. Pittsburgh, PA
  "The Challenges of Designing 3D Microarchitectures"  
08/2006 Hongkong University of Science and Technology Hong Kong, China
  "3D Microarchitecture Design"  
08/2006 Intel China Research Center Beijing, China
  "3D Microarchitecture Design"  
03/2006 IBM T.J.Watson Research Center. Yorktown, NY
  "The Challenges of Designing 3D Microarchitectures"