Brief introduction:
In order to explore the 3D cache design space, we develop
a 3D cache delay-energy estimation tool called 3DCACTI. Our tool is built on top of the Cacti 3.0 2D cache tool (Cache
Access and Cycle Time). 3DCACTI estimats the optimum access times, and power dissipation of a cache using 3D IC technology for a given
number of active device layers and methodology of partitioning across device layers for various technology nodes. Based on the estimation, 3DCACTI searches for the
optimized configuration that provides the best delay, power,and area efficiency trade-off according to the cost function for
a given number of different 3D partitions.
Enhancements to 2D Cacti:
- Delay models: To model the resistance and capacitance of the 3D vias, we add the RC delay to implement the intra-array partitioning. The resistance of 3D via is estimated to be 10E-8 ohm-cm2 based on actual resistance measurement, and the capacitance is estimated as the capacitance of a 1 micrometer by 1 micrometer contact using top metal layer and the height of the interlayer via is assumed to be 10 micrometer.
- Layout parameters: Several configuration parameters are used in the original Cacti to divide a cache into sub-arrays to achieve delay, energy, and area efficiency trade-offs. In our implementation, two additional parameters, Nx and Ny, are added to model the sub-array level 3D partitions. Nx refers to the number of 3D partitions by dividing wordlines; and Ny refers to the number of 3D partitions by dividing bitlines.
- Technology parameter: The scaling of the delay in transistors is different from that in wires. The original Cacti is built based on the technology parameters of 0.8 micrometer technology.
To estimate the delay and energy for smaller technologies, instead of applying the linear scaling on the final delay and energy numbers as in Cacti, we apply more accurate scaling rules derived from the literature on each individual technology
parameter. We also assume the use of copper interconnect for technologies smaller than 0.18 micronmeter and account for the fact that aspect ratio of 6T SRAM is getting smaller as technology scales. We also adopt the wide-bit cell design
for technologies smaller than 70 nm according to the SRAM design fabricated in 65 nm. We use the transistor sizes scaled from original Cacti and insert repeaters where there are long wires or large
loadings. The sizes of all transistors and repeaters are coupled with the configuration information to account for the transistor counts to estimate total leakage power.
We highlight the portions of 3DCacti that are different from the original Cacti 3.0.
Package Download:
3DCacti package is provided here for download.
Related Publications:
- [TVLSI07] Yuh-fang
Tsai, Feng Wang, Yuan Xie,
N. Vijaykrishnan, M. J.
Irwin. "Design Space Exploration
for Three-Dimensional Cache". To
appear in IEEE
Transactions on
VLSI.
- [JETC06] Yuan Xie,
Gabriel Loh, Bryan Black, and Kerry Bernstein, "Design Space Exploration for 3D Architecture."[PDF]; ACM
Journal of Emerging Technologies for Computer Systems, Vol. 2. No. 2, pp.65-103, April 2006.
- [ISCA06] F. Li, C. Nicopoulos, T. Richardson, Yuan Xie, N. Vijaykrishnan,
and M. Kandemir, "Design and Management of 3D Chip Multiprocessors using Network-in-memory." [PDF 670KB]; Proceedings of the Annual International Symposium on Computer Architecture (ISCA), pp. 130-141, June. 2006. (31 papers accepted out of 234 submissions. 13% acceptance rate)
- [ICCD05] Y-F. Tsai, Yuan
Xie, N. Vijaykrishnan,and Mary J. Irwin, "Three-Dimensional Cache Design Exploration Using 3DCacti." [PDF]; Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 519-524, Oct. 2005.